On 27/03/2023 11:30, Varadarajan Narayanan wrote:
> Add USB phy and controller related nodes
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
> ---
> Changes in v4:
> - Use newer bindings without subnodes
> - Fix coding style issues
>
> Changes in v3:
> - Insert the nodes at proper location
>
> Changes in v2:
> - Fixed issues flagged by Krzysztof
> - Fix issues reported by make dtbs_check
> - Remove NOC related clocks (to be added with proper
> interconnect support)
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 2bb4053..5379c25 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -215,6 +215,45 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + qusb_phy_0: phy@7b000 {
> + compatible = "qcom,ipq9574-qusb2-phy";
> + reg = <0x0007b000 0x180>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&xo_board_clk>;
> + clock-names = "cfg_ahb",
> + "ref";
> +
> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> + status = "disabled";
> + };
> +
> + ssphy_0: phy@7d000 {
> + compatible = "qcom,ipq9574-qmp-usb3-phy";
> + reg = <0x0007d000 0xa00>;
> + #clock-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
Why do you need these three?
> +
> + clocks = <&gcc GCC_USB0_AUX_CLK>,
> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&gcc GCC_USB0_PIPE_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "pipe";
> +
> + resets = <&gcc GCC_USB0_PHY_BCR>,
> + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> + reset-names = "phy",
> + "common";
> + status = "disabled";
> +
> + #phy-cells = <0>;
> + clock-output-names = "usb0_pipe_clk";
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
> + };
> +
> pcie0_phy: phy@84000 {
> compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> reg = <0x00084000 0x1bc>; /* Serdes PLL */
> @@ -436,6 +475,50 @@
> status = "disabled";
> };
>
> + usb3: usb3@8a00000 {
usb@
> + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> + reg = <0x08af8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_SLEEP_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +
> + clock-names = "sys_noc_axi",
> + "anoc_axi",
> + "master",
> + "sleep",
> + "mock_utmi";
> +
> + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + assigned-clock-rates = <200000000>,
> + <24000000>;
> +
> + resets = <&gcc GCC_USB_BCR>;
> + status = "disabled";
> +
> + dwc_0: usb@8a00000 {
> + compatible = "snps,dwc3";
> + reg = <0x8a00000 0xcd00>;
> + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + clock-names = "ref";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&qusb_phy_0>, <&ssphy_0>;
> + phy-names = "usb2-phy", "usb3-phy";
> + tx-fifo-resize;
> + snps,is-utmi-l1-suspend;
> + snps,hird-threshold = /bits/ 8 <0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_u3_susphy_quirk;
> + dr_mode = "host";
Are you saying that peripheral mode cannot work on this USB controller?
Never?
Best regards,
Krzysztof
