Re: [PATCH v2 6/9] arm64: dts: qcom: sc7280: switch USB+DP QMP PHY to new style of bindings

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On 27/03/2023 11:12, Neil Armstrong wrote:
On 26/03/2023 01:57, Dmitry Baryshkov wrote:
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
  arch/arm64/boot/dts/qcom/sc7280.dtsi | 57 +++++++++-------------------
  1 file changed, 18 insertions(+), 39 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 5e6f9f441f1a..887c490bdd14 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -18,6 +18,7 @@
  #include <dt-bindings/interconnect/qcom,sc7280.h>
  #include <dt-bindings/interrupt-controller/arm-gic.h>
  #include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
  #include <dt-bindings/power/qcom-rpmpd.h>
  #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  #include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -3327,49 +3328,26 @@ usb_2_hsphy: phy@88e4000 {
              resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
          };
-        usb_1_qmpphy: phy-wrapper@88e9000 {
-            compatible = "qcom,sc7280-qmp-usb3-dp-phy",
-                     "qcom,sm8250-qmp-usb3-dp-phy";
-            reg = <0 0x088e9000 0 0x200>,
-                  <0 0x088e8000 0 0x40>,
-                  <0 0x088ea000 0 0x200>;
+        usb_1_qmpphy: phy@88e8000 {
+            compatible = "qcom,sc7280-qmp-usb3-dp-phy";
+            reg = <0 0x088e8000 0 0x3000>;
              status = "disabled";
-            #address-cells = <2>;
-            #size-cells = <2>;
-            ranges;
              clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
                   <&rpmhcc RPMH_CXO_CLK>,
-                 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
-            clock-names = "aux", "ref_clk_src", "com_aux";
+                 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+                 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+            clock-names = "aux",
+                      "ref",
+                      "com_aux",
+                      "usb3_pipe";
              resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
                   <&gcc GCC_USB3_PHY_PRIM_BCR>;
              reset-names = "phy", "common";
-            usb_1_ssphy: usb3-phy@88e9200 {
-                reg = <0 0x088e9200 0 0x200>,
-                      <0 0x088e9400 0 0x200>,
-                      <0 0x088e9c00 0 0x400>,
-                      <0 0x088e9600 0 0x200>,
-                      <0 0x088e9800 0 0x200>,
-                      <0 0x088e9a00 0 0x100>;
-                #clock-cells = <0>;
-                #phy-cells = <0>;
-                clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
-                clock-names = "pipe0";
-                clock-output-names = "usb3_phy_pipe_clk_src";
-            };
-
-            dp_phy: dp-phy@88ea200 {
-                reg = <0 0x088ea200 0 0x200>,
-                      <0 0x088ea400 0 0x200>,
-                      <0 0x088eaa00 0 0x200>,
-                      <0 0x088ea600 0 0x200>,
-                      <0 0x088ea800 0 0x200>;
-                #phy-cells = <0>;
-                #clock-cells = <1>;
-            };
+            #clock-cells = <1>;
+            #phy-cells = <1>;
          };
          usb_2: usb@8cf8800 {
@@ -3694,7 +3672,7 @@ usb_1_dwc3: usb@a600000 {
                  iommus = <&apps_smmu 0xe0 0x0>;
                  snps,dis_u2_susphy_quirk;
                  snps,dis_enblslpm_quirk;
-                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+                phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
                  phy-names = "usb2-phy", "usb3-phy";
                  maximum-speed = "super-speed";
              };
@@ -3799,8 +3777,8 @@ dispcc: clock-controller@af00000 {
                   <&gcc GCC_DISP_GPLL0_CLK_SRC>,
                   <&mdss_dsi_phy 0>,
                   <&mdss_dsi_phy 1>,
-                 <&dp_phy 0>,
-                 <&dp_phy 1>,
+                 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+                 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
                   <&mdss_edp_phy 0>,
                   <&mdss_edp_phy 1>;

The gcc usb3_phy_wrapper_gcc_usb30_pipe_clk entry is missing, it was already missing with legacy bindings.

Point noted, it should probably go into a separate change.


Neil

              clock-names = "bi_tcxo",
@@ -4138,8 +4116,9 @@ mdss_dp: displayport-controller@ae90000 {
                          "stream_pixel";
                  assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
                            <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
-                assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
-                phys = <&dp_phy>;
+                assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+                             <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+                phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
                  phy-names = "dp";
                  operating-points-v2 = <&dp_opp_table>;


--
With best wishes
Dmitry




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