On Fri, Mar 24, 2023 at 05:24:37AM +0300, Dmitry Baryshkov wrote:
> Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml)
> to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare
> the child PHY node or split resource regions.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 299 ------------------
> .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 213 +++++++++++--
> 2 files changed, 187 insertions(+), 325 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> index ef49efbd0a20..328588448c6b 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> @@ -16,10 +16,23 @@ description:
> properties:
> compatible:
> enum:
> + - qcom,ipq6018-qmp-pcie-phy
> + - qcom,ipq8074-qmp-gen3-pcie-phy
> + - qcom,ipq8074-qmp-pcie-phy
> + - qcom,msm8998-qmp-pcie-phy
> + - qcom,sc8180x-qmp-pcie-phy
> - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> - qcom,sc8280xp-qmp-gen3x4-pcie-phy
> + - qcom,sdm845-qhp-pcie-phy
> + - qcom,sdm845-qmp-pcie-phy
> + - qcom,sdx55-qmp-pcie-phy
> + - qcom,sm8250-qmp-gen3x1-pcie-phy
> + - qcom,sm8250-qmp-gen3x2-pcie-phy
> + - qcom,sm8250-qmp-modem-pcie-phy
> - qcom,sm8350-qmp-gen3x1-pcie-phy
> + - qcom,sm8450-qmp-gen3x1-pcie-phy
> + - qcom,sm8450-qmp-gen4x2-pcie-phy
> - qcom,sm8550-qmp-gen3x2-pcie-phy
> - qcom,sm8550-qmp-gen4x2-pcie-phy
>
> @@ -28,18 +41,12 @@ properties:
> maxItems: 2
>
> clocks:
> - minItems: 5
> + minItems: 3
> maxItems: 6
>
> clock-names:
> - minItems: 5
> - items:
> - - const: aux
> - - const: cfg_ahb
> - - const: ref
> - - const: rchng
> - - const: pipe
> - - const: pipediv2
> + minItems: 3
> + maxItems: 6
>
> power-domains:
> maxItems: 1
> @@ -50,9 +57,7 @@ properties:
>
> reset-names:
> minItems: 1
> - items:
> - - const: phy
> - - const: phy_nocsr
> + maxItems: 2
>
> vdda-phy-supply: true
>
> @@ -83,11 +88,8 @@ required:
> - reg
> - clocks
> - clock-names
> - - power-domains
> - resets
> - reset-names
> - - vdda-phy-supply
> - - vdda-pll-supply
> - "#clock-cells"
> - clock-output-names
> - "#phy-cells"
> @@ -119,21 +121,116 @@ allOf:
> compatible:
> contains:
> enum:
> - - qcom,sm8350-qmp-gen3x1-pcie-phy
> - - qcom,sm8550-qmp-gen3x2-pcie-phy
> - - qcom,sm8550-qmp-gen4x2-pcie-phy
> + - qcom,msm8998-qmp-pcie-phy
> then:
> properties:
> clocks:
> - maxItems: 5
> + maxItems: 4
> clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: pipe
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: phy
> + - const: common
Reset name looks wrong here too.
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq6018-qmp-pcie-phy
> + - qcom,ipq8074-qmp-gen3-pcie-phy
> + - qcom,ipq8074-qmp-pcie-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: pipe
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: phy
> + - const: common
Same here.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc8180x-qmp-pcie-phy
> + - qcom,sdm845-qhp-pcie-phy
> + - qcom,sdm845-qmp-pcie-phy
> + - qcom,sdx55-qmp-pcie-phy
> + - qcom,sm8250-qmp-gen3x1-pcie-phy
> + - qcom,sm8250-qmp-gen3x2-pcie-phy
> + - qcom,sm8250-qmp-modem-pcie-phy
> + - qcom,sm8450-qmp-gen3x1-pcie-phy
> + - qcom,sm8450-qmp-gen4x2-pcie-phy
> + then:
> + properties:
> + clocks:
> maxItems: 5
> - else:
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: refgen
This one should be named 'rchng' and this set a strict subset of the
sc8280xp clocks.
> + - const: pipe
> + resets:
> + maxItems: 1
> + reset-names:
> + items:
> + - const: phy
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sm8350-qmp-gen3x1-pcie-phy
> + - qcom,sm8550-qmp-gen3x2-pcie-phy
> + resets:
> + minItems: 1
> + reset-names:
> + items:
> + - const: phy
> + then:
> properties:
> clocks:
> - minItems: 6
> + maxItems: 5
> clock-names:
> - minItems: 6
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: rchng
> + - const: pipe
> + resets:
> + maxItems: 1
> + reset-names:
> + items:
> + - const: phy
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
>
> - if:
> properties:
> @@ -143,16 +240,53 @@ allOf:
> - qcom,sm8550-qmp-gen4x2-pcie-phy
> then:
> properties:
> + clocks:
> + maxItems: 5
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: rchng
> + - const: pipe
> resets:
> minItems: 2
> reset-names:
> - minItems: 2
> - else:
> + items:
> + - const: phy
> + - const: phy_nocsr
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> + - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> + - qcom,sc8280xp-qmp-gen3x4-pcie-phy
> + then:
> properties:
> + clocks:
> + minItems: 6
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: rchng
> + - const: pipe
> + - const: pipediv2
> resets:
> - maxItems: 1
> + minItems: 1
> reset-names:
> - maxItems: 1
> + items:
> + - const: phy
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
>
> examples:
> - |
> @@ -213,3 +347,30 @@ examples:
>
> #phy-cells = <0>;
> };
> + - |
> + #define GCC_PCIE1_PHY_REFGEN_CLK 47
> + #define GCC_PCIE_PHY_AUX_CLK 71
> + #define GCC_PCIE_WIGIG_CLKREF_EN 74
> +
> + phy@1c0e000 {
> + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
> + reg = <0x01c0e000 0x1c0>;
> +
> + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
> + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
> + <&gcc GCC_PCIE_1_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe";
> +
> + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> + reset-names = "phy";
> +
> + vdda-phy-supply = <&vreg_l10c_0p88>;
> + vdda-pll-supply = <&vreg_l6b_1p2>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_1_pipe_clk";
> +
> + #phy-cells = <0>;
> + };
This example also looks redundant.
Johan
