The GPU core clock requires that both VDDGX and VDDMX domains are scaled
at the same rate at the same time (well, MX just before GX but you get
the idea). Set MX as parent of GX to take care of that.
Suggested-by: Bjorn Andersson <andersson@xxxxxxxxxx>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
---
drivers/soc/qcom/rpmpd.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
index 2027c820caa7..84283719853c 100644
--- a/drivers/soc/qcom/rpmpd.c
+++ b/drivers/soc/qcom/rpmpd.c
@@ -216,18 +216,22 @@ static struct rpmpd gfx_s2b_vfc = {
.key = KEY_FLOOR_CORNER,
};
+static struct rpmpd mx_rwmx0_lvl;
static struct rpmpd gx_rwgx0_lvl_ao;
static struct rpmpd gx_rwgx0_lvl = {
.pd = { .name = "gx", },
.peer = &gx_rwgx0_lvl_ao,
.res_type = RPMPD_RWGX,
+ .parent = &mx_rwmx0_lvl.pd,
.res_id = 0,
.key = KEY_LEVEL,
};
+static struct rpmpd mx_rwmx0_lvl_ao;
static struct rpmpd gx_rwgx0_lvl_ao = {
.pd = { .name = "gx_ao", },
.peer = &gx_rwgx0_lvl,
+ .parent = &mx_rwmx0_lvl_ao.pd,
.active_only = true,
.res_type = RPMPD_RWGX,
.res_id = 0,
--
2.39.2
