There is only one PCIe PHY in this SoC, so there is no need to add an
index to the suffix. This also matches the naming convention of the PCIe
controller.
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
---
arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 2 +-
arch/arm/boot/dts/qcom-sdx55.dtsi | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
index ad74ecc2a196..81f33eba39e5 100644
--- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
+++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
@@ -242,7 +242,7 @@ &ipa {
status = "okay";
};
-&pcie0_phy {
+&pcie_phy {
status = "okay";
vdda-phy-supply = <&vreg_l1e_bb_1p2>;
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index 7fa542249f1a..bd4edceaa1f4 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -335,7 +335,7 @@ pcie_ep: pcie-ep@1c00000 {
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
- phys = <&pcie0_lane>;
+ phys = <&pcie_lane>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
@@ -343,7 +343,7 @@ pcie_ep: pcie-ep@1c00000 {
status = "disabled";
};
- pcie0_phy: phy@1c07000 {
+ pcie_phy: phy@1c07000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
reg = <0x01c07000 0x1c4>;
#address-cells = <1>;
@@ -363,7 +363,7 @@ pcie0_phy: phy@1c07000 {
status = "disabled";
- pcie0_lane: lanes@1c06000 {
+ pcie_lane: lanes@1c06000 {
reg = <0x01c06000 0x104>, /* tx0 */
<0x01c06200 0x328>, /* rx0 */
<0x01c07200 0x1e8>, /* pcs */
--
2.25.1
