Re: [PATCH 6/6] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

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On 3/6/2023 4:02 PM, Konrad Dybcio wrote:

On 6.03.2023 06:25, Rohit Agarwal wrote:
Enable PCIe Endpoint controller on the SDX65 MTP board based
on Qualcomm SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx>
---
  arch/arm/boot/dts/qcom-sdx65-mtp.dts | 46 ++++++++++++++++++++++++++++++++++++
  1 file changed, 46 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 86bb853..952de105 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -252,6 +252,14 @@
  	vdda-pll-supply = <&vreg_l4b_0p88>;
  };
+&pcie_ep {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
+			&pcie_ep_wake_default>;
status last

pinctrl-n goes before pinctrl-names
+};
+
  &qpic_bam {
  	status = "okay";
  };
@@ -276,6 +284,44 @@
  	memory-region = <&mpss_adsp_mem>;
  };
++&tlmm {
+	pcie_ep_clkreq_default: pcie_ep_clkreq_default {
No underscores in node names, pinctrl children node names
must end in -state. Please check your patches against
"make dtbs_check"
+		mux {
+			pins = "gpio56";
+			function = "pcie_clkreq";
+		};
+		config {
+			pins = "gpio56";
+			drive-strength = <2>;
+			bias-disable;
+		};
mux {} / config {} is unnecessary. You can simply do:

{
     pins = "gpio56";
     function = "pcie_clkreq";
     drive-strength = <2>;
     bias-disable;
};
Thanks for detailed explanation. Will rectify all in the next version.

Thanks,
Rohit.
Konrad
+	};
+
+	pcie_ep_perst_default: pcie_ep_perst_default {
+		mux {
+			pins = "gpio57";
+			function = "gpio";
+		};
+		config {
+			pins = "gpio57";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
+	pcie_ep_wake_default: pcie_ep_wake_default {
+		mux {
+			pins = "gpio53";
+			function = "gpio";
+		};
+		config {
+			pins = "gpio53";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+};
+
  &usb {
  	status = "okay";
  };



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