Add the APCS & A73 PLL nodes to support CPU frequency scaling
Co-developed-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx>
Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx>
Signed-off-by: Devi Priya <quic_devipriy@xxxxxxxxxxx>
---
Changes in V2:
- No changes
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 70d920400265..d20f3c7383f5 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -405,6 +405,24 @@
};
};
+ apcs_glb: mailbox@b111000 {
+ compatible = "qcom,ipq9574-apcs-apps-global",
+ "qcom,ipq6018-apcs-apps-global";
+ reg = <0x0b111000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&a73pll>, <&xo_board_clk>;
+ clock-names = "pll", "xo";
+ #mbox-cells = <1>;
+ };
+
+ a73pll: clock@b116000 {
+ compatible = "qcom,ipq9574-a73pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo_board_clk>;
+ clock-names = "xo";
+ };
+
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
--
2.17.1
