On 23-02-08 17:40:03, Johan Hovold wrote:
> On Mon, Feb 06, 2023 at 05:11:01PM +0200, Abel Vesa wrote:
> > On 23-02-03 10:49:24, Johan Hovold wrote:
> > > On Fri, Feb 03, 2023 at 10:18:05AM +0200, Abel Vesa wrote:
> > > > Add compatible for both PCIe found on SM8550.
> > > > Also add the cnoc_pcie_sf_axi clock needed by the SM8550.
> > >
> > > nit: You're now also adding 'noc_aggr'
> > >
> > > > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> > > > Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
> > > > Reviewed-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
> > > > ---
>
> > > > @@ -182,10 +182,10 @@ struct qcom_pcie_resources_2_3_3 {
> > > >
> > > > /* 6 clocks typically, 7 for sm8250 */
> > > > struct qcom_pcie_resources_2_7_0 {
> > > > - struct clk_bulk_data clks[12];
> > > > + struct clk_bulk_data clks[14];
> > > > int num_clks;
> > > > struct regulator_bulk_data supplies[2];
> > > > - struct reset_control *pci_reset;
> > > > + struct reset_control *rst;
> > >
> > > Please name this one 'reset' or 'resets' (e.g. to avoid hard to parse
> > > things like res->rst below).
> >
> > Well, it would then be inconsitent with 2_3_3 and 2_9_0, which both use
> > rst.
>
> Yeah, I saw that. Fortunately these resources are completely
> independent, but whatever.
Will do it in the next version then.
>
> > > > };
> > > >
> > > > struct qcom_pcie_resources_2_9_0 {
> > > > @@ -1177,9 +1177,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
> > > > unsigned int idx;
> > > > int ret;
> > > >
> > > > - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
> > > > - if (IS_ERR(res->pci_reset))
> > > > - return PTR_ERR(res->pci_reset);
> > > > + res->rst = devm_reset_control_array_get_exclusive(dev);
> > > > + if (IS_ERR(res->rst))
> > > > + return PTR_ERR(res->rst);
> > >
> > > So the reset array implementation apparently both asserts and deasserts
> > > the resets in the order specified in DT (i.e. does not deassert in
> > > reverse order).
> > >
> > > Is that ok also for the new "pci" and "link_down" resets?
> >
> > According to the HPG, yes, this is perfectly fine. It specifically says
> > to assert the pcie reset and then continues saying to assert the
> > link_down reset.
>
> Ok, but that doesn't really say anything about whether it's ok to
> *deassert* them in the same order, which was what I asked about.
Actually, what I wanted to say is that the HPG says something like this:
"assert pcie reset, then assert link_down"
and then at the end it literaly repeats the same phrase.
>
> Johan
