On 23-02-03 11:03:05, Johan Hovold wrote: > On Fri, Feb 03, 2023 at 10:18:04AM +0200, Abel Vesa wrote: > > Add the SM8550 platform to the binding. > > > > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > > --- > > > > This patchset relies on the following patchset: > > https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@xxxxxxxxxx/ > > > > The v6 of this patch is: > > https://lore.kernel.org/all/20230202123902.3831491-10-abel.vesa@xxxxxxxxxx/ > > > > Changes since v6: > > * none > > > > Changes since v5: > > * added Krzysztof's R-b tag > > > > Changes since v4: > > * dropped _serdes infix from ln_shrd table name and from every ln_shrd > > variable name > > * added hyphen between "no CSR" in both places > > * dropped has_ln_shrd_serdes_tbl > > * reordered qmp_pcie_offsets_v6_20 by struct members > > * added rollback for no-CSR reset in qmp_pcie_init fail path > > * moved ln_shrd offset calculation after port_b > > * dropped the minItems for interconnects > > * made iommu related properties global > > * renamed noc_aggr_4 back to noc_aggr > > > > Changes since v3: > > * renamed noc_aggr to noc_aggr_4, as found in the driver > > > > Changes since v2: > > * dropped the pipe from clock-names > > * removed the pcie instance number from aggre clock-names comment > > * renamed aggre clock-names to noc_aggr > > * dropped the _pcie infix from cnoc_pcie_sf_axi > > * renamed pcie_1_link_down_reset to simply link_down > > * added enable-gpios back, since pcie1 node will use it > > > > Changes since v1: > > * Switched to single compatible for both PCIes (qcom,pcie-sm8550) > > * dropped enable-gpios property > > * dropped interconnects related properties, the power-domains > > * properties > > and resets related properties the sm8550 specific allOf:if:then > > * dropped pipe_mux, phy_pipe and ref clocks from the sm8550 specific > > allOf:if:then clock-names array and decreased the minItems and > > maxItems for clocks property accordingly > > * added "minItems: 1" to interconnects, since sm8550 pcie uses just one, > > same for interconnect-names > > > + enable-gpios: > > + description: GPIO controlled connection to ENABLE# signal > > + maxItems: 1 > > What is this gpio used for? Describing it as "ENABLE#" looks wrong as > AFAIK it's not part of the PCIe interface. Oups, that should've been dropped here as well, as I did in the dts/dtsi patches. > > There's also no driver support being adding for this gpio as part of > this series and you don't use it for either controller on the MTP. > > Are you relying on firmware to enable this one currently perhaps? > > > + > > perst-gpios: > > description: GPIO controlled connection to PERST# signal > > maxItems: 1 > > Johan
