This series adds support for the APSS clock to bump the CPU frequency above 800MHz. APSS PLL found in the IPQ5332 is of type Stromer Plus. However the existing IPQ targets uses the Huayra PLL. So the driver has to refactored to accommodate the different PLL types. The first patch in the series does the refactoring, which can be independenty merged. For the Stromer PLL separate function clk_stromer_pll_configure is introduced, so the 3rd patch in the series depends on the below patch https://lore.kernel.org/linux-arm-msm/20230120082631.22053-1-quic_kathirav@xxxxxxxxxxx/ DTS patch depends on the IPQ5332 baseport series https://lore.kernel.org/linux-arm-msm/20230130114702.20606-1-quic_kathirav@xxxxxxxxxxx/ Kathiravan T (6): clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible clk: qcom: apss-ipq-pll: add support for IPQ5332 dt-bindings: mailbox: qcom: add compatible for the IPQ5332 SoC mailbox: qcom-apcs-ipc: add IPQ5332 APSS clock support arm64: dts: qcom: ipq5332: enable the CPUFreq support .../bindings/clock/qcom,a53pll.yaml | 1 + .../mailbox/qcom,apcs-kpss-global.yaml | 3 + arch/arm64/boot/dts/qcom/ipq5332.dtsi | 36 ++++++ drivers/clk/qcom/apss-ipq-pll.c | 111 +++++++++++++++--- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + 5 files changed, 133 insertions(+), 19 deletions(-) -- 2.34.1
