Quoting Kathiravan T (2022-12-27 05:25:07)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index f9e4cfd7261c..29866100df08 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -204,9 +204,24 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_CONFIG_CTL] = 0x1C,
> [PLL_OFF_STATUS] = 0x20,
> },
> + [CLK_ALPHA_PLL_TYPE_STROMER] = {
> + [PLL_OFF_L_VAL] = 0x08,
> + [PLL_OFF_ALPHA_VAL] = 0x10,
> + [PLL_OFF_ALPHA_VAL_U] = 0x14,
> + [PLL_OFF_USER_CTL] = 0x18,
> + [PLL_OFF_USER_CTL_U] = 0x1c,
> + [PLL_OFF_CONFIG_CTL] = 0x20,
> + [PLL_OFF_CONFIG_CTL_U] = 0xff,
> + [PLL_OFF_TEST_CTL] = 0x30,
> + [PLL_OFF_TEST_CTL_U] = 0x34,
> + [PLL_OFF_STATUS] = 0x28,
> + },
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>
> +static unsigned long
> +alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
Is this necessary?
> + u32 alpha_width);
> /*
> * Even though 40 bits are present, use only 32 for ease of calculation.
> */
> @@ -215,6 +230,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> #define ALPHA_BITWIDTH 32U
> #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
>
> +#define ALPHA_PLL_STATUS_REG_SHIFT 8
> +
> #define PLL_HUAYRA_M_WIDTH 8
> #define PLL_HUAYRA_M_SHIFT 8
> #define PLL_HUAYRA_M_MASK 0xff
> @@ -325,7 +342,7 @@ static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
> void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> const struct alpha_pll_config *config)
> {
> - u32 val, mask;
> + u32 val, val_u, mask, mask_u;
>
> regmap_write(regmap, PLL_L_VAL(pll), config->l);
> regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> @@ -355,14 +372,85 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> mask |= config->pre_div_mask;
> mask |= config->post_div_mask;
> mask |= config->vco_mask;
> + mask |= config->alpha_en_mask;
> + mask |= config->alpha_mode_mask;
>
> regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
>
> + /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
Instead of adding these things to clk_alpha_pll_configure() can you
introduce another api like clk_stromer_pll_configure() that sets these
values unconditionally? That way we don't have to think or worry about
the other alpha PLLs (of which there are many).
> + val_u = config->status_reg_val << ALPHA_PLL_STATUS_REG_SHIFT;
> + val_u |= config->lock_det;
> +
> + mask_u = config->status_reg_mask;
> + mask_u |= config->lock_det;
> +
> + if (val_u)
> + regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
> +
> + if (config->test_ctl_val)
> + regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
> +
> + if (config->test_ctl_hi_val)
> + regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
> +
> if (pll->flags & SUPPORTS_FSM_MODE)
> qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
> }
> EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
>
> +static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + u32 l;
> + u64 a;
> +
> + req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
> + &l, &a, ALPHA_REG_BITWIDTH);
> +
> + return 0;
> +}
> +
> +static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long prate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + u32 l;
> + int ret;
> + u64 a;
> +
> + rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
> +
> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
> + a >> ALPHA_BITWIDTH);
> +
> + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
> + PLL_ALPHA_EN, PLL_ALPHA_EN);
> +
> + if (!clk_hw_is_enabled(hw))
> + return 0;
> +
> + /*
> + * Stromer PLL supports Dynamic programming.
> + * It allows the PLL frequency to be changed on-the-fly without first
> + * execution of a shutdown procedure followed by a bring up procedure.
> + */
> +
Drop newline above please.
> + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
> + PLL_UPDATE);
> +
> + ret = wait_for_pll_update(pll);
> + if (ret)
> + return ret;
> +
> + ret = wait_for_pll_enable_lock(pll);
> + if (ret)
> + return ret;
> +
> + return 0;
Just use
return wait_for_pll_enable_lock(pll);
> +}
> +
> static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
> {
> int ret;
> @@ -1013,6 +1101,16 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
>
> +const struct clk_ops clk_alpha_pll_stromer_ops = {
> + .enable = clk_alpha_pll_enable,
> + .disable = clk_alpha_pll_disable,
> + .is_enabled = clk_alpha_pll_is_enabled,
> + .recalc_rate = clk_alpha_pll_recalc_rate,
> + .determine_rate = clk_alpha_pll_stromer_determine_rate,
> + .set_rate = clk_alpha_pll_stromer_set_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
> +
> const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
> .enable = clk_trion_pll_enable,
> .disable = clk_trion_pll_disable,
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index 2bdae362c827..1d122919e275 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -1,5 +1,5 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> -/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
> +/* Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved. */
2022 or 2023?
