Re: [PATCH 04/13] clk: qcom: cpu-8996: support using GPLL0 as SMUX input

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On 11/01/2023 22:59, Konrad Dybcio wrote:


On 11.01.2023 20:19, Dmitry Baryshkov wrote:
In some cases the driver might need using GPLL0 to drive CPU clocks.
Bring it in through the sys_apcs_aux clock.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
Oh that's new.. downstream doesn't talk about this..

It does, but under the hood of the init procedure. See:

        /* Select GPLL0 for 300MHz for the perf cluster */
        writel_relaxed(0xC, vbases[APC1_BASE] + MUX_OFFSET);



Konrad
  drivers/clk/qcom/clk-cpu-8996.c | 12 ++++++++++++
  1 file changed, 12 insertions(+)

diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index d51965fda56d..0e0c00d44c6f 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -12,6 +12,8 @@
   *                              +-------+
   *               XO             |       |
   *           +------------------>0      |
+ *               SYS_APCS_AUX   |       |
+ *           +------------------>3      |
   *                              |       |
   *                    PLL/2     | SMUX  +----+
   *                      +------->1      |    |
@@ -310,20 +312,29 @@ static const struct clk_ops clk_cpu_8996_pmux_ops = {
  	.determine_rate = clk_cpu_8996_pmux_determine_rate,
  };
+static const struct parent_map smux_parent_map[] = {
+	{ .cfg = 0, }, /* xo */
+	{ .cfg = 1, }, /* pll */
+	{ .cfg = 3, }, /* sys_apcs_aux */
+};
+
  static const struct clk_parent_data pwrcl_smux_parents[] = {
  	{ .fw_name = "xo" },
  	{ .hw = &pwrcl_pll_postdiv.hw },
+	{ .fw_name = "sys_apcs_aux" },
  };
static const struct clk_parent_data perfcl_smux_parents[] = {
  	{ .fw_name = "xo" },
  	{ .hw = &perfcl_pll_postdiv.hw },
+	{ .fw_name = "sys_apcs_aux" },
  };
static struct clk_regmap_mux pwrcl_smux = {
  	.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
  	.shift = 2,
  	.width = 2,
+	.parent_map = smux_parent_map,
  	.clkr.hw.init = &(struct clk_init_data) {
  		.name = "pwrcl_smux",
  		.parent_data = pwrcl_smux_parents,
@@ -337,6 +348,7 @@ static struct clk_regmap_mux perfcl_smux = {
  	.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
  	.shift = 2,
  	.width = 2,
+	.parent_map = smux_parent_map,
  	.clkr.hw.init = &(struct clk_init_data) {
  		.name = "perfcl_smux",
  		.parent_data = perfcl_smux_parents,

--
With best wishes
Dmitry




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