Quoting Srinivasa Rao Mandadapu (2023-01-04 08:21:37)
> The clock gating control for TX/RX/WSA core bus clocks would be required
> to be reset(moved from hardware control) from audio core driver. Thus
> add the support for the reset clocks in audioreach based clock driver.
>
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@xxxxxxxxxxx>
> ---
> drivers/clk/qcom/lpasscc-sc7280.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
> index 85dd5b9..1efb72d 100644
> --- a/drivers/clk/qcom/lpasscc-sc7280.c
> +++ b/drivers/clk/qcom/lpasscc-sc7280.c
> @@ -12,10 +12,12 @@
> #include <linux/regmap.h>
>
> #include <dt-bindings/clock/qcom,lpass-sc7280.h>
> +#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
>
> #include "clk-regmap.h"
> #include "clk-branch.h"
> #include "common.h"
> +#include "reset.h"
>
> static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
> .halt_reg = 0x0,
> @@ -102,6 +104,18 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
> .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
> };
>
> +static const struct qcom_reset_map lpass_cc_sc7280_resets[] = {
> + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
> + [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
> + [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
Why are we adding these resets again? These are already exposed in
lpassaudiocc-sc7280.c
