Re: [PATCH 3/9] interconnect: qcom: sc7180: drop IP0 remnants

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On 06/01/2023 15:44, Alex Elder wrote:
On 1/6/23 1:33 AM, Dmitry Baryshkov wrote:
Drop two defines leftover from the commit 2f3724930eb4 ("interconnect:
qcom: sc7180: Drop IP0 interconnects"), which dropped handling of the
IP0 resource in favour of handling it in the clk-rpmh driver.

Fixes: 2f3724930eb4 ("interconnect: qcom: sc7180: Drop IP0 interconnects")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>

On this patch and the rest like it in this series, I suggest
adding a comment that indicates why there's a gap in the simple
numeric sequence.

Ok, sounds fair.

Feel free to ignore this if you don't think
this is a good idea.  I'll give examples below, although I
don't fully understand why there's a master and slave on the
interconnect, but just a single clock for RPMH clock...

Well, interconnects is a about paths between nodes. So even if we have to cast a vote on a single resource, there should be two nodes.


                     -Alex

---
  drivers/interconnect/qcom/sc7180.h | 2 --
  1 file changed, 2 deletions(-)

diff --git a/drivers/interconnect/qcom/sc7180.h b/drivers/interconnect/qcom/sc7180.h
index c6212a10c2f6..b691d97d56cf 100644
--- a/drivers/interconnect/qcom/sc7180.h
+++ b/drivers/interconnect/qcom/sc7180.h
@@ -11,7 +11,6 @@
  #define SC7180_MASTER_APPSS_PROC            0
  #define SC7180_MASTER_SYS_TCU                1
  #define SC7180_MASTER_NPU_SYS                2
-#define SC7180_MASTER_IPA_CORE                3
     /* MASTER_IPA_CORE (4) is represented as an RPMH clock */
  #define SC7180_MASTER_LLCC                4
  #define SC7180_MASTER_A1NOC_CFG                5
  #define SC7180_MASTER_A2NOC_CFG                6
@@ -58,7 +57,6 @@
  #define SC7180_MASTER_USB3                47
  #define SC7180_MASTER_EMMC                48
  #define SC7180_SLAVE_EBI1                49
-#define SC7180_SLAVE_IPA_CORE                50
     /* SLAVE_IPA_CORE (50) is represented as an RPMH clock */
  #define SC7180_SLAVE_A1NOC_CFG                51
  #define SC7180_SLAVE_A2NOC_CFG                52
  #define SC7180_SLAVE_AHB2PHY_SOUTH            53


--
With best wishes
Dmitry




[Index of Archives]     [Linux ARM Kernel]     [Linux ARM]     [Linux Omap]     [Fedora ARM]     [Linux for Sparc]     [IETF Annouce]     [Security]     [Bugtraq]     [Linux MIPS]     [ECOS]     [Asterisk Internet PBX]     [Linux API]

  Powered by Linux