On 05/01/2023 14:41, Dmitry Baryshkov wrote: > Define clock/clock-names properties of the GCC device node to be used > on APQ8084 platform. > > Note: the driver uses a single pcie_pipe clock, however most probably > there are two pipe clocks, one from each of PCIe QMP PHYs. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > --- > .../bindings/clock/qcom,gcc-apq8084.yaml | 48 +++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml > index 8ade176c24f4..732b6770b46e 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml > @@ -25,6 +25,30 @@ properties: > compatible: > const: qcom,gcc-apq8084 > > + clocks: > + items: > + - description: XO source > + - description: Sleep clock source > + - description: UFS RX symbol 0 clock > + - description: UFS RX symbol 1 clock > + - description: UFS TX symbol 0 clock > + - description: UFS TX symbol 1 clock > + - description: SATA ASIC0 clock > + - description: SATA RX clock > + - description: PCIe PIPE clock > + > + clock-names: > + items: > + - const: xo > + - const: sleep_clk > + - const: ufs_rx_symbol_0_clk_src > + - const: ufs_rx_symbol_1_clk_src > + - const: ufs_tx_symbol_0_clk_src > + - const: ufs_tx_symbol_1_clk_src > + - const: sata_asic0_clk > + - const: sata_rx_clk > + - const: pcie_pipe > + > required: > - compatible > > @@ -32,11 +56,35 @@ unevaluatedProperties: false > > examples: > - | > + /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */ > + #define UFS_PHY_RX_SYMBOL_0 0 > + #define UFS_PHY_RX_SYMBOL_1 1 > + #define UFS_PHY_TX_SYMBOL_0 2 Use numbers in example instead. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
