Add reset control memory region in lpasscc reg property for
ADSP enabled platforms.
Also add "qcom,adsp-pil-mode" for herobrine crd revision 3
board specific device tree.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
Tested-by: Mohammad Rafi Shaik <quic_mohs@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 4 ++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
index 7583c3c..2a619b4 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
@@ -178,3 +178,7 @@
reg = <0 0x033c0000 0x0 0x20000>,
<0 0x03550000 0x0 0xa100>;
};
+
+&lpasscc {
+ qcom,adsp-pil-mode;
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f10a663..a52008f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2226,11 +2226,13 @@
lpasscc: lpasscc@3000000 {
compatible = "qcom,sc7280-lpasscc";
reg = <0 0x03000000 0 0x40>,
- <0 0x03c04000 0 0x4>;
- reg-names = "qdsp6ss", "top_cc";
+ <0 0x03c04000 0 0x4>,
+ <0 0x032a9000 0 0x1000>;
+ reg-names = "qdsp6ss", "top_cc", "reset_cgcr";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
+ #reset-cells = <1>;
};
lpass_rx_macro: codec@3200000 {
--
2.7.4
