Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for audioreach based SC7280 platforms.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
Tested-by: Mohammad Rafi Shaik <quic_mohs@xxxxxxxxxxx>
---
.../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 97c6bd9..054c496 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -31,15 +31,20 @@ properties:
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
reg:
items:
- description: LPASS qdsp6ss register
- description: LPASS top-cc register
+ - description: LPASS reset-cgcr register
reg-names:
items:
- const: qdsp6ss
- const: top_cc
+ - const: reset_cgcr
qcom,adsp-pil-mode:
description:
@@ -62,11 +67,14 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@3000000 {
compatible = "qcom,sc7280-lpasscc";
- reg = <0x03000000 0x40>, <0x03c04000 0x4>;
- reg-names = "qdsp6ss", "top_cc";
+ reg = <0x03000000 0x40>,
+ <0x03c04000 0x4>,
+ <0x032a9000 0x1000>;
+ reg-names = "qdsp6ss", "top_cc", "reset_cgcr";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
qcom,adsp-pil-mode;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
...
--
2.7.4
