On 28/12/2022 12:30, Krzysztof Kozlowski wrote:
On 27/12/2022 02:32, Dmitry Baryshkov wrote:Define clock/clock-names properties of the GCC device node to be used on APQ8084 platform. Note: the driver uses a single pcie_pipe clock, however most probably there are two pipe clocks, one from each of PCIe QMP PHYs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> --- .../bindings/clock/qcom,gcc-apq8084.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml index 8ade176c24f4..02a856f14fbe 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml @@ -25,6 +25,30 @@ properties: compatible: const: qcom,gcc-apq8084+ clocks:+ items: + - description: XO source + - description: Sleep clock source + - description: UFS RX symbol 0 clock + - description: UFS RX symbol 1 clock + - description: UFS TX symbol 0 clock + - description: UFS TX symbol 1 clock + - description: SATA ASIC0 clock + - description: SATA RX clock + - description: PCIe PIPE clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: ufs_rx_symbol_0_clk_src + - const: ufs_rx_symbol_1_clk_src + - const: ufs_tx_symbol_0_clk_src + - const: ufs_tx_symbol_1_clk_src + - const: sata_asic0_clk + - const: sata_rx_clk + - const: pcie_pipe + required: - compatible@@ -38,5 +62,24 @@ examples:#clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + + clocks = <&xo_board>, + <&sleep_clk>, + <&ufsphy 0>,No IDs available yet?
No. I didn't add IDs to the UFS symbol patchset. And anyway apq8084 seems to use different amount of UFS symbol clocks (4, while other platforms use just 3).
-- With best wishes Dmitry
