On 28.12.2022 14:32, Dmitry Baryshkov wrote:
> The test clock apparently it's not used by anyone upstream. Remove it.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> drivers/clk/qcom/gcc-sm8150.c | 17 -----------------
> 1 file changed, 17 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index 09cf827addab..70b067f3618c 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -26,7 +26,6 @@
> enum {
> P_BI_TCXO,
> P_AUD_REF_CLK,
> - P_CORE_BI_PLL_TEST_SE,
> P_GPLL0_OUT_EVEN,
> P_GPLL0_OUT_MAIN,
> P_GPLL7_OUT_MAIN,
> @@ -117,14 +116,12 @@ static const struct parent_map gcc_parent_map_0[] = {
> { P_BI_TCXO, 0 },
> { P_GPLL0_OUT_MAIN, 1 },
> { P_GPLL0_OUT_EVEN, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 },
> };
>
> static const struct clk_parent_data gcc_parents_0[] = {
> { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> { .hw = &gpll0.clkr.hw },
> { .hw = &gpll0_out_even.clkr.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map gcc_parent_map_1[] = {
> @@ -132,7 +129,6 @@ static const struct parent_map gcc_parent_map_1[] = {
> { P_GPLL0_OUT_MAIN, 1 },
> { P_SLEEP_CLK, 5 },
> { P_GPLL0_OUT_EVEN, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 },
> };
>
> static const struct clk_parent_data gcc_parents_1[] = {
> @@ -140,41 +136,34 @@ static const struct clk_parent_data gcc_parents_1[] = {
> { .hw = &gpll0.clkr.hw },
> { .fw_name = "sleep_clk", .name = "sleep_clk" },
> { .hw = &gpll0_out_even.clkr.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map gcc_parent_map_2[] = {
> { P_BI_TCXO, 0 },
> { P_SLEEP_CLK, 5 },
> - { P_CORE_BI_PLL_TEST_SE, 7 },
> };
>
> static const struct clk_parent_data gcc_parents_2[] = {
> { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> { .fw_name = "sleep_clk", .name = "sleep_clk" },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map gcc_parent_map_3[] = {
> { P_BI_TCXO, 0 },
> { P_GPLL0_OUT_MAIN, 1 },
> - { P_CORE_BI_PLL_TEST_SE, 7 },
> };
>
> static const struct clk_parent_data gcc_parents_3[] = {
> { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> { .hw = &gpll0.clkr.hw },
> - { .fw_name = "core_bi_pll_test_se"},
> };
>
> static const struct parent_map gcc_parent_map_4[] = {
> { P_BI_TCXO, 0 },
> - { P_CORE_BI_PLL_TEST_SE, 7 },
> };
>
> static const struct clk_parent_data gcc_parents_4[] = {
> { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map gcc_parent_map_5[] = {
> @@ -182,7 +171,6 @@ static const struct parent_map gcc_parent_map_5[] = {
> { P_GPLL0_OUT_MAIN, 1 },
> { P_GPLL7_OUT_MAIN, 3 },
> { P_GPLL0_OUT_EVEN, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 },
> };
>
> static const struct clk_parent_data gcc_parents_5[] = {
> @@ -190,7 +178,6 @@ static const struct clk_parent_data gcc_parents_5[] = {
> { .hw = &gpll0.clkr.hw },
> { .hw = &gpll7.clkr.hw },
> { .hw = &gpll0_out_even.clkr.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map gcc_parent_map_6[] = {
> @@ -198,7 +185,6 @@ static const struct parent_map gcc_parent_map_6[] = {
> { P_GPLL0_OUT_MAIN, 1 },
> { P_GPLL9_OUT_MAIN, 2 },
> { P_GPLL0_OUT_EVEN, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 },
> };
>
> static const struct clk_parent_data gcc_parents_6[] = {
> @@ -206,7 +192,6 @@ static const struct clk_parent_data gcc_parents_6[] = {
> { .hw = &gpll0.clkr.hw },
> { .hw = &gpll9.clkr.hw },
> { .hw = &gpll0_out_even.clkr.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map gcc_parent_map_7[] = {
> @@ -214,7 +199,6 @@ static const struct parent_map gcc_parent_map_7[] = {
> { P_GPLL0_OUT_MAIN, 1 },
> { P_AUD_REF_CLK, 2 },
> { P_GPLL0_OUT_EVEN, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 },
> };
>
> static const struct clk_parent_data gcc_parents_7[] = {
> @@ -222,7 +206,6 @@ static const struct clk_parent_data gcc_parents_7[] = {
> { .hw = &gpll0.clkr.hw },
> { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
> { .hw = &gpll0_out_even.clkr.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
