On Tue, Dec 06, 2022 at 10:51:40AM +0100, Robert Marko wrote: > On Mon, 5 Dec 2022 at 22:52, Bjorn Andersson <andersson@xxxxxxxxxx> wrote: > > > > On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote: > > > IPQ8074 comes in 2 silicon versions: > > > * v1 with 2x Gen2 PCIe ports and QMP PHY-s > > > * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s > > > > > > v2 is the final and production version that is actually supported by the > > > kernel, however it looks like PCIe related nodes were added for the v1 SoC. > > > > > > Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support > > > by fixing the Gen3 QMP PHY node first. > > > > > > Change the compatible to the Gen3 QMP PHY, correct the register space start > > > and size, add the missing misc PCS register space. > > > > > > > Does this imply that the current node doesn't actually work? > > Hi Bjorn, > Yes, the node is for a completely different PHY generation, basically > PCIe on IPQ8074 > is completely broken, hence this patch series. > > > > > If that's the case, could we perhaps adopt Johan Hovolds' new binding > > and drop the subnode in favor of just a flat reg covering the whole > > QMP region? > > I have not seen that so far, any examples? > See Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in v6.2-rc1. The idea is to, at least, use this for all new platforms introduced. And if the current definition doesn't actually work I suggest that we replace it with the new one. Regards, Bjorn
