On Tue, 27 Dec 2022 at 14:08, Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> wrote:
>
>
>
> On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> > Add clocks and clock-names nodes to the gcc device to bind clocks using
> > the DT links.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> > ---
> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
>
> Though - again at the end of reviewing - I noticed you could have
> gone .index instead, like with qcs404.
QCS404 driver was in a good shape, so I doubt there will be any
significant changes for the bindings. On the other hand the apq8084 is
in such a flux state, that I can easily imagine getting additional
clock parents and/or removing existing parents. This can better be
coped with by using the clock-names instead of indices. For example,
see my comment regarding the pcie pipe clocks. I fear that apq8084 was
not seriously touched for the last 5 years. And even back in those
days not everything was plumbed together. None of MMCC (and thus
display, camera, venus), SATA, PCIe are present in the
qcom-apq8084.dtsi.
>
> Konrad
>
> > arch/arm/boot/dts/qcom-apq8084.dtsi | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
> > index fe30abfff90a..815b6c53f7b8 100644
> > --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
> > +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
> > @@ -388,6 +388,24 @@ gcc: clock-controller@fc400000 {
> > #reset-cells = <1>;
> > #power-domain-cells = <1>;
> > reg = <0xfc400000 0x4000>;
> > + clocks = <&xo_board>,
> > + <&sleep_clk>,
> > + <0>, /* ufs */
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>, /* sata */
> > + <0>,
> > + <0>; /* pcie */
> > + clock-names = "xo",
> > + "sleep_clk",
> > + "ufs_rx_symbol_0_clk_src",
> > + "ufs_rx_symbol_1_clk_src",
> > + "ufs_tx_symbol_0_clk_src",
> > + "ufs_tx_symbol_1_clk_src",
> > + "sata_asic0_clk",
> > + "sata_rx_clk",
> > + "pcie_pipe";
> > };
> >
> > tcsr_mutex: hwlock@fd484000 {
--
With best wishes
Dmitry
