On 22/12/2022 10:42, Srinivasa Rao Mandadapu wrote:
> Update lpasscc register mapping for avoiding memory regions conflict with
> ADSP pil node.
>
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> index 0ce8755..a750f05 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> @@ -111,6 +111,14 @@
> };
> };
>
> +&lpasscc {
> + reg = <0 0x03c04000 0 0x4>,
> + <0 0x032a9000 0 0x1000>;
Misaligned.
> + reg-names = "top_cc", "reset-cgcr";
I have doubts this was tested... git grep shows 0 answers.
> + #reset-cells = <1>;
Why all these are not part of SoC DTSI?
> + status = "okay";
Why?
> +};
> +
> &soc {
> qcom,lpass@3000000 {
> compatible = "qcom,sc7280-adsp-pil";
Best regards,
Krzysztof
