From: Vinod Koul <vkoul@xxxxxxxxxx> Add the spmi bus as found in the SM8450 SoC Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list] Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> --- I took over this patch from Vinod, it was submitted long long ago: https://lore.kernel.org/lkml/20211209103505.197453-1-vkoul@xxxxxxxxxx/ arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..b9b59c5223eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2715,6 +2715,28 @@ aoss_qmp: power-controller@c300000 { #clock-cells = <0>; }; + spmi_bus: spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x00003000>, + <0 0x0c500000 0 0x00400000>, + <0 0x0c440000 0 0x00080000>, + <0 0x0c4c0000 0 0x00010000>, + <0 0x0c42d000 0 0x00010000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + ipcc: mailbox@ed18000 { compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; reg = <0 0x0ed18000 0 0x1000>; -- 2.39.0
