On Mon, Dec 12, 2022 at 06:02:58PM +0530, Manivannan Sadhasivam wrote:
> The Qualcomm LLCC/EDAC drivers were using a fixed register stride for
> accessing the (Control and Status Regsiters) CSRs of each LLCC bank.
> This offset only works for some SoCs like SDM845 for which driver support
> was initially added.
>
> But the later SoCs use different register stride that vary between the
> banks with holes in-between. So it is not possible to use a single register
> stride for accessing the CSRs of each bank. By doing so could result in a
> crash with the current drivers. So far this crash is not reported since
> EDAC_QCOM driver is not enabled in ARM64 defconfig and no one tested the
> driver extensively by triggering the EDAC IRQ (that's where each bank
> CSRs are accessed).
>
> For fixing this issue, let's obtain the base address of each LLCC bank from
> devicetree and get rid of the fixed stride.
>
> This series affects multiple platforms but I have only tested this on
> SM8250 and SM8450. Testing on other platforms is welcomed.
>
Tested-by: Andrew Halaney <ahalaney@xxxxxxxxxx> # sa8540p-ride
I took this for a quick spin on the qdrive3 I've got access to without
any issue:
[root@localhost ~]# modprobe qcom_edac
[root@localhost ~]# dmesg | grep -i edac
[ 0.620723] EDAC MC: Ver: 3.0.0
[ 1.165417] ghes_edac: GHES probing device list is empty
[ 594.688103] EDAC DEVICE0: Giving out device to module qcom_llcc_edac controller llcc: DEV qcom_llcc_edac (INTERRUPT)
[root@localhost ~]# cat /proc/interrupts | grep ecc
174: 0 0 0 0 0 0 0 0 GICv3 614 Level llcc_ecc
[root@localhost ~]#
Potentially stupid question, but are users expected to manually load the
driver as I did? I don't see how it would be loaded automatically in the
current state, but thought it was funny that I needed to modprobe
myself.
Please let me know if you want me to do any more further testing!
Thanks,
Andrew
