On Wed, Dec 07, 2022 at 04:49:07PM +0200, Dmitry Baryshkov wrote:
> On 05/12/2022 19:44, Bjorn Andersson wrote:
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
[..]
> > +static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x494,
> > + .features = 0,
> > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
>
> ubwc_swizzle ? I'd suppose it's 6, but I'd bet on it.
>
I don't see ubwc_swizzle defined for any other platform, and it seems to
be unused for DPU_HW_UBWC_VER_40. Am I perhaps missing something?
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20},
> > + },
> > +};
> > +
> > static const struct dpu_mdp_cfg qcm2290_mdp[] = {
> > {
> > .name = "top_0", .id = MDP_TOP,
> > @@ -648,6 +693,45 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
> > },
> > };
> > +static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
> > + {
> > + .name = "ctl_0", .id = CTL_0,
> > + .base = 0x15000, .len = 0x204,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG),
>
> Please use CTL_SC7270_MASK instead, unless you have a strong reasong not to
> do it.
>
No strong reason, will update.
Thanks,
Bjorn
