On Tue, Dec 06, 2022 at 12:55:06AM +0300, Dmitry Baryshkov wrote:
>
>
> On 1 December 2022 20:43:14 GMT+03:00, Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> wrote:
> >SM8350 default init sequence sets some PCS registers to HS G3, thereby
> >disabling HS G4 mode. This has the effect on MPHY capability negotiation
> >between the host and the device during link startup and causes the
> >PA_MAXHSGEAR to G3 irrespective of device max gear.
> >
> >Due to that, the agreed gear speed determined by the UFS core will become
> >G3 only and the platform won't run at G4.
> >
> >So, let's remove setting these registers for SM8350 as like other G4
> >compatible platforms. One downside of this is that, when the board design
> >uses non-G4 compatible device, then MPHY will continue to run in the
>
> QMP PHY?
>
No. MPHY is the actual IP that does the negotiation.
> >default mode (G4) even if UFSHCD runs in G3. But this is the case for
> >other platforms as well.
>
> Should this be fixed by adding a separate set of tables used to setup g3?
>
The default table is G3 only but the issue here is that, with these register
writes, the UFS device PA_MAXHSGEAR register becomes G3 only during MPHY
negotiation. So the host cannot scale up to G4 even if the UFSHCD supports it.
Thanks,
Mani
>
> >
> >Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> >---
> > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 -------
> > 1 file changed, 7 deletions(-)
> >
> >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >index d5324c4e8513..6c7c6a06fe3b 100644
> >--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >@@ -567,13 +567,6 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > };
>
> --
> With best wishes
> Dmitry
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