On 23.11.2022 00:12, Dmitry Baryshkov wrote:
> In preparation to adding the sm8350 and sm8450 PHYs support, rearrange
> register values calculations in dsi_7nm_phy_enable(). This change bears
> no functional changes itself, it is merely a preparation for the next
> patch.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 26 +++++++++++------------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 9e7fa7d88ead..0b780f9d3d0a 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -858,23 +858,34 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> /* Alter PHY configurations if data rate less than 1.5GHZ*/
> less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
>
> + if (phy->cphy_mode) {
> + vreg_ctrl_0 = 0x51;
> + vreg_ctrl_1 = 0x55;
> + glbl_pemph_ctrl_0 = 0x11;
> + lane_ctrl0 = 0x17;
> + } else {
> + vreg_ctrl_1 = 0x5c;
> + glbl_pemph_ctrl_0 = 0x00;
> + lane_ctrl0 = 0x1f;
> + }
> +
> if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> if (phy->cphy_mode) {
> glbl_rescode_top_ctrl = 0x00;
> glbl_rescode_bot_ctrl = 0x3c;
> } else {
> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
> }
> glbl_str_swi_cal_sel_ctrl = 0x00;
> glbl_hstx_str_ctrl_0 = 0x88;
> } else {
> - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
> if (phy->cphy_mode) {
> glbl_str_swi_cal_sel_ctrl = 0x03;
> glbl_hstx_str_ctrl_0 = 0x66;
> } else {
> + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
> glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
> glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
> }
> @@ -882,17 +893,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> glbl_rescode_bot_ctrl = 0x3c;
> }
>
> - if (phy->cphy_mode) {
> - vreg_ctrl_0 = 0x51;
> - vreg_ctrl_1 = 0x55;
> - glbl_pemph_ctrl_0 = 0x11;
> - lane_ctrl0 = 0x17;
> - } else {
> - vreg_ctrl_1 = 0x5c;
> - glbl_pemph_ctrl_0 = 0x00;
> - lane_ctrl0 = 0x1f;
> - }
> -
> /* de-assert digital and pll power down */
> data = BIT(6) | BIT(5);
> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
