On Wed, 23 Nov 2022 at 03:30, Stephen Boyd <sboyd@xxxxxxxxxx> wrote:
>
> Quoting Robert Marko (2022-11-16 13:46:55)
> > It appears that having only .name populated in parent_data for clocks
> > which are only globally searchable currently will not work as the clk core
> > won't copy that name if there is no .fw_name present as well.
> >
> > So, populate .fw_name for all parent clocks in parent_data.
> >
> > Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
> >
> > Co-developed-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
> > Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
> > Signed-off-by: Robert Marko <robimarko@xxxxxxxxx>
> > ---
> > Changes in v2:
> > * Add fw_name for PCIe PHY pipe clocks as well
> > ---
> > drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
> > 1 file changed, 26 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
> > index d231866804f6..8374cc40915a 100644
> > --- a/drivers/clk/qcom/gcc-ipq8074.c
> > +++ b/drivers/clk/qcom/gcc-ipq8074.c
> > @@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src = {
> > };
> >
> > static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
> > - { .name = "pcie20_phy0_pipe_clk" },
> > + { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
>
> Is there a DT binding update for these firmware names?
Hi Stephen,
I have that name documented as part of series for passing the QMP
PCI output clock directly to GCC instead of global matching that
I wanted to send after this and PCI fixups were merged.
I can change it to match the global name, but that is a bit confusing
as pcie20_phy0_pipe_clk is actually from the Gen3 PHY but the GCC
driver was made for v1 of the SoC which was pre-production and then
it got updated to support v2 which is only supported so the name stuck
as it would break backwards compatibility.
Regards,
Robert
