On 11/11/2022 17:22, Johan Hovold wrote:
On Thu, Nov 10, 2022 at 12:06:45PM +0100, Konrad Dybcio wrote:
On 10/11/2022 11:35, Johan Hovold wrote:
Enable the NVMe SSD connected to PCIe2.
Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 63 +++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+ pcie2a_default: pcie2a-default-state {
Aren't they going to be identical for all boards anyway? Maybe there
could be some commonization..
We had that discussion and decided that keeping the pinconfig in the dts
is the right thing to do.
And even if the clkreq pin will be the same for all boards that's not
necessarily the case for the other two.
Okay then. I simply keep forgetting which pins we concluded go where..
Konrad
+ clkreq-n-pins {
+ pins = "gpio142";
+ function = "pcie2a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup0_i2c4_default: qup0-i2c4-default-state {
pins = "gpio171", "gpio172";
function = "qup4";
Johan
