On Tue, Nov 08, 2022 at 08:42:17PM +0100, Robert Marko wrote:
> It appears that having only .name populated in parent_data for clocks
> which are only globally searchable currently will not work as the clk core
> won't copy that name if there is no .fw_name present as well.
>
While we want to migrate users to .fw_name and .index, that sounds like
a bug. Where does this (not) happen?
Regards,
Bjorn
> So, populate .fw_name for all parent clocks in parent_data.
>
> Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
>
> Co-developed-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
> Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
> Signed-off-by: Robert Marko <robimarko@xxxxxxxxx>
> ---
> drivers/clk/qcom/gcc-ipq8074.c | 48 +++++++++++++++++-----------------
> 1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
> index d231866804f6..bf64aa683605 100644
> --- a/drivers/clk/qcom/gcc-ipq8074.c
> +++ b/drivers/clk/qcom/gcc-ipq8074.c
> @@ -1137,7 +1137,7 @@ static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
>
> static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
> { .fw_name = "xo", .name = "xo" },
> - { .name = "bias_pll_nss_noc_clk" },
> + { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
> { .hw = &gpll0.clkr.hw },
> { .hw = &gpll2.clkr.hw },
> };
> @@ -1362,7 +1362,7 @@ static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
>
> static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
> { .fw_name = "xo", .name = "xo" },
> - { .name = "bias_pll_cc_clk" },
> + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
> { .hw = &gpll0.clkr.hw },
> { .hw = &gpll4.clkr.hw },
> { .hw = &nss_crypto_pll.clkr.hw },
> @@ -1413,10 +1413,10 @@ static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
>
> static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
> { .fw_name = "xo", .name = "xo" },
> - { .name = "uniphy0_gcc_rx_clk" },
> - { .name = "uniphy0_gcc_tx_clk" },
> + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
> + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
> { .hw = &ubi32_pll.clkr.hw },
> - { .name = "bias_pll_cc_clk" },
> + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
> };
>
> static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
> @@ -1465,10 +1465,10 @@ static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
>
> static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
> { .fw_name = "xo", .name = "xo" },
> - { .name = "uniphy0_gcc_tx_clk" },
> - { .name = "uniphy0_gcc_rx_clk" },
> + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
> + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
> { .hw = &ubi32_pll.clkr.hw },
> - { .name = "bias_pll_cc_clk" },
> + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
> };
>
> static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
> @@ -1696,12 +1696,12 @@ static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
>
> static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
> { .fw_name = "xo", .name = "xo" },
> - { .name = "uniphy0_gcc_rx_clk" },
> - { .name = "uniphy0_gcc_tx_clk" },
> - { .name = "uniphy1_gcc_rx_clk" },
> - { .name = "uniphy1_gcc_tx_clk" },
> + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
> + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
> + { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
> + { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
> { .hw = &ubi32_pll.clkr.hw },
> - { .name = "bias_pll_cc_clk" },
> + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
> };
>
> static const struct parent_map
> @@ -1758,12 +1758,12 @@ static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
>
> static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
> { .fw_name = "xo", .name = "xo" },
> - { .name = "uniphy0_gcc_tx_clk" },
> - { .name = "uniphy0_gcc_rx_clk" },
> - { .name = "uniphy1_gcc_tx_clk" },
> - { .name = "uniphy1_gcc_rx_clk" },
> + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
> + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
> + { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
> + { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
> { .hw = &ubi32_pll.clkr.hw },
> - { .name = "bias_pll_cc_clk" },
> + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
> };
>
> static const struct parent_map
> @@ -1820,10 +1820,10 @@ static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
>
> static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
> { .fw_name = "xo", .name = "xo" },
> - { .name = "uniphy2_gcc_rx_clk" },
> - { .name = "uniphy2_gcc_tx_clk" },
> + { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
> + { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
> { .hw = &ubi32_pll.clkr.hw },
> - { .name = "bias_pll_cc_clk" },
> + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
> };
>
> static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
> @@ -1877,10 +1877,10 @@ static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
>
> static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
> { .fw_name = "xo", .name = "xo" },
> - { .name = "uniphy2_gcc_tx_clk" },
> - { .name = "uniphy2_gcc_rx_clk" },
> + { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
> + { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
> { .hw = &ubi32_pll.clkr.hw },
> - { .name = "bias_pll_cc_clk" },
> + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
> };
>
> static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
> --
> 2.38.1
>
