On Thu, Nov 03, 2022 at 10:28:32AM +0530, Sibi Sankar wrote: > Add support for the SCMI QTI memlat (memory latency) vendor protocol. > The QTI memlat vendor protocol takes in several tuneables including the > IPM ratio (Instructions Per Miss), bus bandwidth requirements and PMU > maps to enable frequency scaling of various buses (L3/LLCC/DDR) performed > by the memory latency governor running on the CPUSS Control Processor. > > Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx> > --- > drivers/firmware/arm_scmi/Kconfig | 10 + > drivers/firmware/arm_scmi/Makefile | 1 + > drivers/firmware/arm_scmi/qcom_memlat_vendor.c | 269 +++++++++++++++++++++++++ > include/linux/scmi_protocol.h | 36 ++++ > 4 files changed, 316 insertions(+) > create mode 100644 drivers/firmware/arm_scmi/qcom_memlat_vendor.c > > diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/Kconfig > index a14f65444b35..814a3fc37dc1 100644 > --- a/drivers/firmware/arm_scmi/Kconfig > +++ b/drivers/firmware/arm_scmi/Kconfig > @@ -136,6 +136,16 @@ config ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE > > endif #ARM_SCMI_PROTOCOL > > +config QTI_SCMI_MEMLAT_PROTOCOL > + tristate "Qualcomm Technologies, Inc. SCMI MEMLAT vendor Protocol" > + depends on ARM_SCMI_PROTOCOL && QCOM_CPUCP_MBOX If you have set the transport correctly, there should be no need for any such dependency. > + help > + The SCMI QTI memlat vendor protocol adds support for the frequency > + scaling of buses (L3/LLCC/DDR) by the QTI HW memlat governor running > + on the CPUSS Control Processor (CPUCP). > + > + Say Y here if you want to build this driver. > + I don't think it is scalable to have a config option for each vendor+protocol Kconfig. IMO just one config for all qcom vendor protocol please. -- Regards, Sudeep
