An HBR3-capable device shall also support TPS4. Since TPS4 feature had been implemented already, it is not necessary to limit link rate at HBR2 (5.4G). This patch remove this limitation to support HBR3 (8.1G) link rate. Signed-off-by: Kuogee Hsieh <quic_khsieh@xxxxxxxxxxx> --- drivers/gpu/drm/msm/dp/dp_panel.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 5149ceb..3344f5a 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -78,10 +78,6 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) if (link_info->num_lanes > dp_panel->max_dp_lanes) link_info->num_lanes = dp_panel->max_dp_lanes; - /* Limit support upto HBR2 until HBR3 support is added */ - if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) - link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); - drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
