On 5.10.2022 16:33, Johan Hovold wrote:
> The GCC_UFS_REF_CLKREF_CLK must be enabled or the second UFS controller
> fails to enumerate on sa8295p-adp.
>
> Note that the vendor kernel enables both GCC_UFS_REF_CLKREF_CLK and
> GCC_UFS_1_CARD_CLKREF_CLK and it is possible that the former should be
> modelled as a parent of the latter. The clock driver also has a
> GCC_UFS_CARD_CLKREF_CLK clock which the firmware appears to enable on
> the ADP.
My guess would be that XBL/whatever other bootloader enables all of them as
it scans for bootable devices and only gates one afterwards..
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
Konrad
>
> The usual lack of documentation for Qualcomm SoCs makes this a highly
> annoying guessing game, but as the second controller works on the ADP
> without either card reference clock enabled, only enable
> GCC_UFS_REF_CLKREF_CLK for now.
>
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
> ---
>
> The related issue for the first controller is being fixed here:
>
> https://lore.kernel.org/lkml/20220830180120.2082734-1-bmasney@xxxxxxxxxx/T/#u
>
> Johan
>
>
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index cf7ef37c11ec..917f1feac6ac 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -960,7 +960,7 @@ ufs_card_phy: phy@1da7000 {
> ranges;
> clock-names = "ref",
> "ref_aux";
> - clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
> + clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
> <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
>
> resets = <&ufs_card_hc 0>;
