Add cpufreq-epss node for the QDU1000 and QRU1000 SoCs
and add references to it from the cpu nodes.
Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 62a6a6e8ca59..2fd449df3706 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -45,6 +45,7 @@ CPU0: cpu@0 {
enable-method = "psci";
power-domain-names = "psci";
power-domains = <&CPU_PD0>;
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -62,6 +63,7 @@ CPU1: cpu@100 {
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
@@ -77,6 +79,7 @@ CPU2: cpu@200 {
enable-method = "psci";
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
@@ -91,6 +94,7 @@ CPU3: cpu@300 {
enable-method = "psci";
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
@@ -246,6 +250,18 @@ uart7: serial@99c000 {
};
};
+ cpufreq_hw: cpufreq@17d91000 {
+ compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss",
+ "qcom,cpufreq-epss";
+ reg = <0x0 0x17d91000 0x0 0x1000>;
+ reg-names = "freq-domain0";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh0_int";
+ #freq-domain-cells = <1>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x1f40000 0x0 0x20000>;
--
2.37.3
