On Wed, Sep 28, 2022 at 10:10:02PM +0300, Dmitry Baryshkov wrote: > On 28/09/2022 18:28, Johan Hovold wrote: > > Since commit 0d58280cf1e6 ("phy: Update PHY power control sequence") the > > PHY is powered on before configuring the registers and only the MSM8996 > > PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS > > initialisation table, may possibly require a second update afterwards. > > > > To make things worse, the POWER_DOWN_CONTROL register lies at a > > different offset on more recent SoCs so that the second update, which > > still used a hard-coded offset, would write to an unrelated register > > (e.g. a revision-id register on SC8280XP). > > > > As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop > > the bogus register update. > > > > Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") added support > > I'm not sure about the particular fixes tag. Backporting from the split > driver into old qmp driver would be a complete pain. That a separate issue. The fixes tag point at the commit introducing the bug. And I didn't add a stable tag on purpose. > > Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> Johan