On Tue, 20 Sep 2022 15:52:22 +0530, Krishna chaitanya chundru wrote:
> Few PCIe endpoints like NVMe and WLANs are always expecting the device
> to be in D0 state and the link to be active (or in l1ss) all the
> time (including in S3 state).
>
> This patch series adds this support for allowing the system to enter
> S3 state (and further low power states) with PCIe Device being in D0
> state and with link being in l1ss on qcom platforms.
>
> [...]
Applied, thanks!
[5/5] clk: qcom: gcc-sc7280: Update the .pwrsts for PCIe GDSC
commit: 1a58ee1330b2cb6d71feb0aaf827cc10030f78b4
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
