On 9/15/2022 7:50 AM, Bjorn Andersson wrote:
On Wed, Sep 14, 2022 at 11:00:17AM +0530, Rajendra Nayak wrote:
USB has a requirement to put a performance state vote on 'cx'
while active. Use 'required-opps' to pass this information from
device tree, and since all the GDSCs in GCC (including USB) are
sub-domains of cx, we also add cx as a power-domain for GCC.
Now when any of the consumers of the GDSCs (in this case USB)
votes on a perforamance state, genpd framework can identify that
the GDSC itself does not support a performance state and it
then propogates the vote to the parent, which in this case is cx.
This change would also mean that any GDSC in GCC thats left enabled
during low power state (perhaps because its marked with a
ALWAYS_ON flag) can prevent the system from entering low power
since that would prevent cx from transitioning to low power.
Ideally any consumers that would need to have their devices
(partially) powered to support wakeups should look at making the
resp. GDSCs transtion to a Retention (PWRSTS_RET) state instead
of leaving them ALWAYS_ON.
Signed-off-by: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
---
* This patch is a follow up based on the discussion on the previously
posted version to support USB performance state voting [1]
* Another patch that this approach depends on is the one to fix the
handling of PWRSTS_RET in the GDSC driver [2] so we can have USB
GDSC transtion to a RET state instead of marking it ALWAYS_ON
[1] https://lore.kernel.org/linux-usb/YTduDqCO9aUyAsw1@ripper/
[2] https://lore.kernel.org/all/20220901101756.28164-1-quic_rjendra@xxxxxxxxxxx/#t
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index ad04025a8a1a..8a21446738bf 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -828,6 +828,7 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ power-domains = <&rpmhpd SC7280_CX>;
};
ipcc: mailbox@408000 {
@@ -3456,6 +3457,7 @@
"ss_phy_irq";
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_svs>;
The patch looks really good, but don't you need &rpmhpd_opp_nom for the
200MHz assigned to GCC_USB30_PRIM_MASTER_CLK?
you are right, I wrote this patch a long while back, not sure if
we were on a lower clock back then, thanks for catching, I will fix it
and repost.
Also, how about adding the same to &usb_2, while we're at it?
Sure, will do that as well. thanks.
Regards,
Bjorn
resets = <&gcc GCC_USB30_PRIM_BCR>;
--
2.17.1
