On Fri, Sep 09, 2022 at 02:14:39PM +0530, Krishna chaitanya chundru wrote: > Add suspend and resume syscore ops. > > When system suspends, and if the link is in L1ss, disable the clocks > and power down the phy so that system enters into low power state by > parking link in L1ss to save the maximum power. And when the system > resumes, enable the clocks back and power on phy if they are disabled > in the suspend path. > > we are doing this only when link is in l1ss but not in L2/L3 as > nowhere we are forcing link to L2/L3 by sending PME turn off. > > is_suspended flag indicates if the clocks are disabled in the suspend > path or not. > > There is access to Ep PCIe space to mask MSI/MSIX after pm suspend ops > (getting hit by affinity changes while making CPUs offline during suspend, > this will happen after devices are suspended (all phases of suspend ops)). > When registered with pm ops there is a crash due to un-clocked access, > as in the pm suspend op clocks are disabled. So, registering with syscore > ops which will called after making CPUs offline. > > Make GDSC always on to ensure controller and its dependent clocks > won't go down during system suspend. > > Krishna chaitanya chundru (5): > PCI: qcom: Add system suspend and resume support > PCI: qcom: Add retry logic for link to be stable in L1ss > phy: core: Add support for phy power down & power up > phy: qcom: Add power down/up callbacks to pcie phy > clk: qcom: Alwaya on pcie gdsc This seems fairly ugly because it doesn't fit nicely into the PM framework. Why is this a qcom-specific thing? What about other DWC-based controllers? > drivers/clk/qcom/gcc-sc7280.c | 2 +- > drivers/pci/controller/dwc/pcie-qcom.c | 156 ++++++++++++++++++++++++++++++- > drivers/phy/phy-core.c | 30 ++++++ > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 50 ++++++++++ > include/linux/phy/phy.h | 20 ++++ > 5 files changed, 256 insertions(+), 2 deletions(-) > > -- > 2.7.4 >
