On Sat, Oct 25, 2014 at 2:22 AM, Marc Zyngier <marc.zyngier@xxxxxxx> wrote: > On Sat, Oct 25 2014 at 12:12:55 am BST, Bjorn Andersson <bjorn@xxxxxxx> wrote: >> On Fri, Oct 24, 2014 at 10:59 AM, Marc Zyngier <marc.zyngier@xxxxxxx> wrote: >>> I just pushed out a branch: >>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git >>> irq/irqchip_state >>> >>> Please let me know if that's useful for you. >>> >> >> I think that my irq_read_line() would be equivalent of >> irq_get_irqchip_state(IRQCHIP_STATE_PENDING), i.e. the state of the >> interrupt ignoring masking. And the rest would be EINVAL. >> So I think this would work out just fine for us! > > Excellent. > Hi Marc, We gave this some more thought and read up on what "pending" and "active" means according to the ARM GIC - PENDING is not what we want :( In the Qualcomm pmic we have two interrupt status registers "interrupt" and "real-time". I think the "interrupt" status register would be the one related to your defined constants. However what we need to access in our use cases are the "real-time" status register, which basically is a representation of the input to the interrupt logic. As far as I can see the GIC does not offer anything like that, but I hope we could add another constant to your enum list and utilise your api for this. I'm not entirely sure what we should call it though, IRQCHIP_STATE_LEVEL seems somewhat conflicting with level trigger and the Qualcomm name IRQCHIP_STATE_REALTIME isn't very self describing. Maybe IRQCHIP_STATE_LINE_LEVEL? Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
