On 9/7/2022 5:52 PM, Krzysztof Kozlowski wrote:
On 03/09/2022 04:13, Krishna chaitanya chundru wrote:Add missing aggre0 and aggre1 clocks. Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> --- changes since v2: - Increase the max items of clock's in common properties. --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12..b759465 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -53,11 +53,11 @@ properties: # Platform constraints are described later. clocks: minItems: 3 - maxItems: 12 + maxItems: 13clock-names:minItems: 3 - maxItems: 12 + maxItems: 13resets:minItems: 1 @@ -423,8 +423,8 @@ allOf: then: properties: clocks: - minItems: 11 - maxItems: 11 + minItems: 13 + maxItems: 13 clock-names: items: - const: pipe # PIPE clock @@ -437,6 +437,8 @@ allOf: - const: bus_slave # Slave AXI clock - const: slave_q2a # Slave Q2A clock - const: tbu # PCIe TBU clock + - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock - const: ddrss_sf_tbu # PCIe SF TBU clockWhy adding them in the middle, not at the end of list? It does not match other variants and affects the DTB ABI (order is strict). Best regards, Krzysztof
Ok I will change the order as suggested.
