On Thu, Sep 01, 2022 at 01:23:06PM +0300, Dmitry Baryshkov wrote:
> In order to make the schema more readable, split dpu-sc7180 into the DPU
> and MDSS parts, each one describing just a single device binding.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> .../bindings/display/msm/dpu-sc7180.yaml | 185 ++++++------------
> .../bindings/display/msm/mdss-sc7180.yaml | 85 ++++++++
> 2 files changed, 146 insertions(+), 124 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/msm/mdss-sc7180.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
> index 47e74f78e939..0ed64fe065c2 100644
> --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
> @@ -9,81 +9,43 @@ title: Qualcomm Display DPU dt properties for SC7180 target
> maintainers:
> - Krishna Manikandan <quic_mkrishn@xxxxxxxxxxx>
>
> -description: |
> - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
> - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> - bindings of MDSS and DPU are mentioned for SC7180 target.
> +description: Device tree bindings for the SC7180 DPU display controller.
I assume this doesn't say anything more than the title, so just drop it.
>
> allOf:
> - - $ref: /schemas/display/msm/mdss-common.yaml#
> + - $ref: /schemas/display/msm/dpu-common.yaml#
>
> properties:
> compatible:
> items:
> - - const: qcom,sc7180-mdss
> + - const: qcom,sc7180-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
>
> clocks:
> items:
> - - description: Display AHB clock from gcc
> - - description: Display AHB clock from dispcc
> + - description: Display hf axi clock
> + - description: Display ahb clock
> + - description: Display rotator clock
> + - description: Display lut clock
> - description: Display core clock
> + - description: Display vsync clock
>
> clock-names:
> items:
> + - const: bus
> - const: iface
> - - const: ahb
> + - const: rot
> + - const: lut
> - const: core
> -
> - iommus:
> - maxItems: 1
> -
> - interconnects:
> - maxItems: 1
> -
> - interconnect-names:
> - maxItems: 1
> -
> -patternProperties:
> - "^display-controller@[0-9a-f]+$":
> - type: object
> - description: Node containing the properties of DPU.
> - unevaluatedProperties: false
> -
> - allOf:
> - - $ref: /schemas/display/msm/dpu-common.yaml#
> -
> - properties:
> - compatible:
> - items:
> - - const: qcom,sc7180-dpu
> -
> - reg:
> - items:
> - - description: Address offset and size for mdp register set
> - - description: Address offset and size for vbif register set
> -
> - reg-names:
> - items:
> - - const: mdp
> - - const: vbif
> -
> - clocks:
> - items:
> - - description: Display hf axi clock
> - - description: Display ahb clock
> - - description: Display rotator clock
> - - description: Display lut clock
> - - description: Display core clock
> - - description: Display vsync clock
> -
> - clock-names:
> - items:
> - - const: bus
> - - const: iface
> - - const: rot
> - - const: lut
> - - const: core
> - - const: vsync
> + - const: vsync
>
> unevaluatedProperties: false
>
> @@ -91,71 +53,46 @@ examples:
> - |
> #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
> #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> - #include <dt-bindings/interrupt-controller/arm-gic.h>
> - #include <dt-bindings/interconnect/qcom,sdm845.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
>
> - display-subsystem@ae00000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "qcom,sc7180-mdss";
> - reg = <0xae00000 0x1000>;
> - reg-names = "mdss";
> - power-domains = <&dispcc MDSS_GDSC>;
> - clocks = <&gcc GCC_DISP_AHB_CLK>,
> - <&dispcc DISP_CC_MDSS_AHB_CLK>,
> - <&dispcc DISP_CC_MDSS_MDP_CLK>;
> - clock-names = "iface", "ahb", "core";
> -
> - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-controller;
> - #interrupt-cells = <1>;
> -
> - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
> - interconnect-names = "mdp0-mem";
> -
> - iommus = <&apps_smmu 0x800 0x2>;
> - ranges;
> -
> - display-controller@ae01000 {
> - compatible = "qcom,sc7180-dpu";
> - reg = <0x0ae01000 0x8f000>,
> - <0x0aeb0000 0x2008>;
> -
> - reg-names = "mdp", "vbif";
> -
> - clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> - <&dispcc DISP_CC_MDSS_AHB_CLK>,
> - <&dispcc DISP_CC_MDSS_ROT_CLK>,
> - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> - <&dispcc DISP_CC_MDSS_MDP_CLK>,
> - <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> - clock-names = "bus", "iface", "rot", "lut", "core",
> - "vsync";
> -
> - interrupt-parent = <&mdss>;
> - interrupts = <0>;
> - power-domains = <&rpmhpd SC7180_CX>;
> - operating-points-v2 = <&mdp_opp_table>;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> - dpu_intf1_out: endpoint {
> - remote-endpoint = <&dsi0_in>;
> - };
> - };
> -
> - port@2 {
> - reg = <2>;
> - dpu_intf0_out: endpoint {
> - remote-endpoint = <&dp_in>;
> - };
> - };
> - };
> - };
> + display-controller@ae01000 {
> + compatible = "qcom,sc7180-dpu";
> + reg = <0x0ae01000 0x8f000>,
> + <0x0aeb0000 0x2008>;
> +
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus", "iface", "rot", "lut", "core",
> + "vsync";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&mdp_opp_table>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + dpu_intf0_out: endpoint {
> + remote-endpoint = <&dp_in>;
> + };
> + };
> + };
> };
> ...
> diff --git a/Documentation/devicetree/bindings/display/msm/mdss-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/mdss-sc7180.yaml
> new file mode 100644
> index 000000000000..27d944f0e471
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/mdss-sc7180.yaml
The preferred naming is using the compatible: qcom,sc7180-mdss.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/mdss-sc7180.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display MDSS dt properties for SC7180 target
Qualcomm SC7180 Display MDSS
> +
> +maintainers:
> + - Krishna Manikandan <quic_mkrishn@xxxxxxxxxxx>
> +
> +description: |
> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> + bindings of MDSS are mentioned for SC7180 target.
> +
> +allOf:
> + - $ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sc7180-mdss
> +
> + clocks:
> + items:
> + - description: Display AHB clock from gcc
> + - description: Display AHB clock from dispcc
> + - description: Display core clock
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: ahb
> + - const: core
> +
> + iommus:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 1
> +
> + interconnect-names:
> + maxItems: 1
> +
> +patternProperties:
> + "^display-controller@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,sc7180-dpu
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interconnect/qcom,sdm845.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + display-subsystem@ae00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "qcom,sc7180-mdss";
> + reg = <0xae00000 0x1000>;
> + reg-names = "mdss";
> + power-domains = <&dispcc MDSS_GDSC>;
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "ahb", "core";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
> + interconnect-names = "mdp0-mem";
> +
> + iommus = <&apps_smmu 0x800 0x2>;
> + ranges;
> + };
> +...
> --
> 2.35.1
>
>
