On 05-08-22, 08:44, Bjorn Andersson wrote: > When the platform was booted with the involved clocks enabled the > clk_set_rate() of the link and pixel clocks will perculate to the > children, which will fail to update because the PHY driver has just shut > down the PLL. > > Postpone the clock rate updates until the PLL is back online to avoid > reconfiguring the clocks while the PLL is not ticking. Applied, thanks This gave me a conflict which I think I have resolved, pls do check Thanks -- ~Vinod
