In preparation of adding the bindings for future SoCs, let's define the
clocks per platform.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
---
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 46 +++++++++++--------
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index b728ede3f09f..83a2cfc63bc1 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -9,9 +9,6 @@ title: Qualcomm PCIe Endpoint Controller binding
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
-allOf:
- - $ref: "pci-ep.yaml#"
-
properties:
compatible:
const: qcom,sdx55-pcie-ep
@@ -35,24 +32,12 @@ properties:
- const: mmio
clocks:
- items:
- - description: PCIe Auxiliary clock
- - description: PCIe CFG AHB clock
- - description: PCIe Master AXI clock
- - description: PCIe Slave AXI clock
- - description: PCIe Slave Q2A AXI clock
- - description: PCIe Sleep clock
- - description: PCIe Reference clock
+ minItems: 7
+ maxItems: 7
clock-names:
- items:
- - const: aux
- - const: cfg
- - const: bus_master
- - const: bus_slave
- - const: slave_q2a
- - const: sleep
- - const: ref
+ minItems: 7
+ maxItems: 7
qcom,perst-regs:
description: Reference to a syscon representing TCSR followed by the two
@@ -112,6 +97,29 @@ required:
- reset-names
- power-domains
+allOf:
+ - $ref: "pci-ep.yaml#"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdx55-pcie-ep
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ clock-names:
+ items:
+ - const: aux # PCIe Auxiliary clock
+ - const: cfg # PCIe CFG AHB clock
+ - const: bus_master # PCIe Master AXI clock
+ - const: bus_slave # PCIe Slave AXI clock
+ - const: slave_q2a # PCIe Slave Q2A AXI clock
+ - const: sleep # PCIe Sleep clock
+ - const: ref # PCIe Reference clock
+
unevaluatedProperties: false
examples:
--
2.25.1
