The Last Level Cache Controller (LLCC) device does not need to access
entire LLCC address space. Currently driver uses only hardware info and
status registers which both reside in LLCC0_COMMON range (offset
0x30000, size 0x1000). Narrow the address space to allow binding other
drivers to rest of LLCC address space.
Cc: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
Cc: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
Reported-by: Steev Klimaszewski <steev@xxxxxxxx>
Suggested-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index fe14f7e7523b..e318c3f8aee0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2048,7 +2048,7 @@ uart15: serial@a9c000 {
llcc: system-cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
+ reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.34.1
