Quoting Satya Priya (2022-07-20 04:03:43)
> From: Taniya Das <quic_tdas@xxxxxxxxxxx>
>
> The clock gating control for TX/RX/WSA core bus clocks would be required
> to be reset(moved from hardware control) from audio core driver. Thus
> add the support for the reset clocks.
>
> Also add the external mclk to interface external MI2S.
>
> Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280").
> Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> ---
> drivers/clk/qcom/lpassaudiocc-sc7280.c | 22 +++++++++++++++++++++-
> drivers/clk/qcom/lpasscorecc-sc7280.c | 33 +++++++++++++++++++++++++++++++++
> 2 files changed, 54 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
> index 6067328..063e036 100644
> --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
> +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
> @@ -23,6 +23,7 @@
> #include "clk-regmap-mux.h"
> #include "common.h"
> #include "gdsc.h"
> +#include "reset.h"
>
> enum {
> P_BI_TCXO,
> @@ -248,7 +249,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
> .parent_data = lpass_aon_cc_parent_data_0,
> .num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
> .flags = CLK_OPS_PARENT_ENABLE,
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
This diff isn't mentioned in the commit text at all. Is it intentional?
If so, please mention why it needs to change.
