Programming of QMP PCIe PHYs slightly differs between RC and EP modes.
Currently both qcom and qcom-ep PCIe controllers setup the PHY in the
default mode, making it impossible to select at runtime whether the PHY
should be running in RC or in EP modes. Usually this is not an issue,
since for most devices only the RC mode is used. Some devices (SDX55)
currently support only the EP mode without supporting the RC mode (at
this moment).
Nevertheless some of the Qualcomm platforms (e.g. the aforementioned
SDX55) would still benefit from being able to switch between RC and EP
depending on the driver being used. While it is possible to use
different compat strings for the PHY depending on the mode, it seems
like an incorrect approach, since the PHY doesn't differ between
usecases. It's the PCIe controller, who should decide how to configure
the PHY.
This patch series implements the ability to select between RC and EP
modes, by allowing the PCIe QMP PHY driver to switch between
programming tables.
Note, there is no direct dependency between PCIe and PHY parts of these
series, so these patches can be merged into respective subsystem trees
separately.
Changes since RFC:
- Fixed the compilation of PCIe EP driver,
- Changed pri/sec names to primary and secondary,
- Added comments regarding usage of secondary_rc/_ep fields.
Dmitry Baryshkov (4):
phy: qcom-qmp-pcie: split register tables into primary and secondary
part
phy: qcom-qmp-pcie: support separate tables for EP mode
PCI: qcom: Setup PHY to work in RC mode
PCI: qcom-ep: Setup PHY to work in EP mode
drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +
drivers/pci/controller/dwc/pcie-qcom.c | 4 +
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 169 +++++++++++++---------
3 files changed, 109 insertions(+), 68 deletions(-)
--
2.35.1
