Add macros for a visually more compact branch clocks definition,
one for the common branch and one for branch_aon. They differ
from ops point of view, like their name suggest. There are also
three different macros to define the clk.hw.init depending on the
number and type of parent passed on as argument. Also, the macros
added here are only the ones used by gcc-sdm845 driver.
More will be added later on.
Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
---
drivers/clk/qcom/clk-branch.h | 82 +++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
index 17a58119165e..a12ffebf0e5f 100644
--- a/drivers/clk/qcom/clk-branch.h
+++ b/drivers/clk/qcom/clk-branch.h
@@ -37,6 +37,88 @@ struct clk_branch {
struct clk_regmap clkr;
};
+#define INIT_QCOM_CC_CLKR_HW_2(_name, _flags, _ops, _fw_name) \
+ { \
+ .name = #_name, \
+ .parent_data = &(const struct clk_parent_data) { \
+ .fw_name = _fw_name, \
+ .name = _fw_name, \
+ }, \
+ .num_parents = 1, \
+ .flags = _flags, \
+ .ops = _ops, \
+ }
+
+#define INIT_QCOM_CC_CLKR_HW_1(_name, _flags, _ops, _parent_hw) \
+ { \
+ .name = #_name, \
+ .parent_data = &(const struct clk_parent_data) { \
+ .hw = _parent_hw, \
+ }, \
+ .num_parents = 1, \
+ .flags = _flags, \
+ .ops = _ops, \
+ }
+
+#define INIT_QCOM_CC_CLKR_HW_0(_name, _flags, _ops, ...) \
+ { \
+ .name = #_name, \
+ .flags = _flags, \
+ .ops = _ops, \
+ }
+
+#define INIT_QCOM_CC_CLKR(_num_parents, _enable_reg, _enable_mask, \
+ _name, _flags, _ops, ...) \
+ { \
+ .enable_reg = _enable_reg, \
+ .enable_mask = _enable_mask, \
+ .hw.init = &(struct clk_init_data) \
+ INIT_QCOM_CC_CLKR_HW_##_num_parents(_name, \
+ _flags, \
+ _ops, __VA_ARGS__), \
+ }
+
+#define __DEFINE_QCOM_CC_CLK_BRANCH(_halt_check, _name, _num_parents, \
+ _halt_reg, \
+ _hwcg_reg, _hwcg_bit, \
+ _enable_reg, _enable_mask, \
+ _flags, _ops, ...) \
+ static struct clk_branch _name = { \
+ .halt_reg = _halt_reg, \
+ .halt_check = BRANCH_##_halt_check, \
+ .hwcg_reg = _hwcg_reg, \
+ .hwcg_bit = _hwcg_bit, \
+ .clkr = INIT_QCOM_CC_CLKR(_num_parents, _enable_reg, \
+ _enable_mask, \
+ _name, _flags, \
+ _ops, __VA_ARGS__), \
+ }
+
+#define DEFINE_QCOM_CC_CLK_BRANCH(_halt_check, _name, _num_parents, \
+ _halt_reg, \
+ _hwcg_reg, _hwcg_bit, \
+ _enable_reg, _enable_mask, \
+ _flags, ...) \
+ __DEFINE_QCOM_CC_CLK_BRANCH(_halt_check, _name, _num_parents, \
+ _halt_reg, \
+ _hwcg_reg, _hwcg_bit, \
+ _enable_reg, _enable_mask, \
+ _flags, \
+ &clk_branch2_ops, __VA_ARGS__)
+
+#define DEFINE_QCOM_CC_CLK_BRANCH_AON(_halt_check, _name, _num_parents, \
+ _halt_reg, \
+ _hwcg_reg, _hwcg_bit, \
+ _enable_reg, _enable_mask, \
+ _flags, ...) \
+ __DEFINE_QCOM_CC_CLK_BRANCH(_halt_check, _name, _num_parents, \
+ _halt_reg, \
+ _hwcg_reg, _hwcg_bit, \
+ _enable_reg, _enable_mask, \
+ _flags, \
+ &clk_branch2_aon_ops, \
+ __VA_ARGS__)
+
extern const struct clk_ops clk_branch_ops;
extern const struct clk_ops clk_branch2_ops;
extern const struct clk_ops clk_branch_simple_ops;
--
2.34.3
