The PCIe QMP PHY requires different programming sequences when being
used for the RC (Root Complex) or for the EP (End Point) modes. Allow
selecting the submode and thus selecting a set of PHY programming
tables.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 33 ++++++++++++++++--------
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 23ca5848c4a8..898288c1cd7d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1368,7 +1368,8 @@ struct qmp_phy_cfg {
/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
struct qmp_phy_cfg_tables pri;
- struct qmp_phy_cfg_tables sec;
+ struct qmp_phy_cfg_tables sec_rc; /* for the RC only */
+ struct qmp_phy_cfg_tables sec_ep; /* for the EP only */
/* clock ids to be requested */
const char * const *clk_list;
@@ -1418,6 +1419,7 @@ struct qmp_phy_cfg {
* @index: lane index
* @qmp: QMP phy to which this lane belongs
* @mode: current PHY mode
+ * @sec: currently selected PHY init table set
*/
struct qmp_phy {
struct phy *phy;
@@ -1433,6 +1435,7 @@ struct qmp_phy {
unsigned int index;
struct qcom_qmp *qmp;
enum phy_mode mode;
+ const struct qmp_phy_cfg_tables *sec;
};
/**
@@ -1683,7 +1686,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
.pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
},
- .sec = {
+ .sec_rc = {
.serdes_tbl = sm8250_qmp_gen3x1_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
.rx_tbl = sm8250_qmp_gen3x1_pcie_rx_tbl,
@@ -1726,7 +1729,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
.pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
.pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
},
- .sec = {
+ .sec_rc = {
.tx_tbl = sm8250_qmp_gen3x2_pcie_tx_tbl,
.tx_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
.rx_tbl = sm8250_qmp_gen3x2_pcie_rx_tbl,
@@ -1951,7 +1954,7 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy)
void __iomem *serdes = qphy->serdes;
qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->pri.serdes_tbl, cfg->pri.serdes_tbl_num);
- qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->sec.serdes_tbl, cfg->sec.serdes_tbl_num);
+ qcom_qmp_phy_pcie_configure(serdes, cfg->regs, qphy->sec->serdes_tbl, qphy->sec->serdes_tbl_num);
return 0;
}
@@ -2045,6 +2048,9 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
unsigned int mask, val, ready;
int ret;
+ if (!qphy->sec)
+ qphy->sec = &cfg->sec_rc;
+
qcom_qmp_phy_pcie_serdes_init(qphy);
ret = clk_prepare_enable(qphy->pipe_clk);
@@ -2057,35 +2063,35 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
cfg->pri.tx_tbl, cfg->pri.tx_tbl_num, 1);
qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
- cfg->sec.tx_tbl, cfg->sec.tx_tbl_num, 1);
+ qphy->sec->tx_tbl, qphy->sec->tx_tbl_num, 1);
/* Configuration for other LANE for USB-DP combo PHY */
if (cfg->is_dual_lane_phy) {
qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
cfg->pri.tx_tbl, cfg->pri.tx_tbl_num, 2);
qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
- cfg->sec.tx_tbl, cfg->sec.tx_tbl_num, 2);
+ qphy->sec->tx_tbl, qphy->sec->tx_tbl_num, 2);
}
qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
cfg->pri.rx_tbl, cfg->pri.rx_tbl_num, 1);
qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
- cfg->sec.rx_tbl, cfg->sec.rx_tbl_num, 1);
+ qphy->sec->rx_tbl, qphy->sec->rx_tbl_num, 1);
if (cfg->is_dual_lane_phy) {
qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
cfg->pri.rx_tbl, cfg->pri.rx_tbl_num, 2);
qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
- cfg->sec.rx_tbl, cfg->sec.rx_tbl_num, 2);
+ qphy->sec->rx_tbl, qphy->sec->rx_tbl_num, 2);
}
qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pri.pcs_tbl, cfg->pri.pcs_tbl_num);
- qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->sec.pcs_tbl, cfg->sec.pcs_tbl_num);
+ qcom_qmp_phy_pcie_configure(pcs, cfg->regs, qphy->sec->pcs_tbl, qphy->sec->pcs_tbl_num);
qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pri.pcs_misc_tbl,
cfg->pri.pcs_misc_tbl_num);
- qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->sec.pcs_misc_tbl,
- cfg->sec.pcs_misc_tbl_num);
+ qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, qphy->sec->pcs_misc_tbl,
+ qphy->sec->pcs_misc_tbl_num);
/*
* Pull out PHY from POWER DOWN state.
@@ -2187,6 +2193,11 @@ static int qcom_qmp_phy_pcie_set_mode(struct phy *phy,
qphy->mode = mode;
+ if (submode)
+ qphy->sec = &qphy->cfg->sec_ep;
+ else
+ qphy->sec = &qphy->cfg->sec_rc;
+
return 0;
}
--
2.35.1
