On 7/1/22 4:24 AM, Bjorn Andersson wrote:
On Sat 14 May 16:54 CDT 2022, Bhupesh Sharma wrote:Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports issues with 'max-frequency' value for ipq8074 sdhci node: arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: mmc@7824900: max-frequency:0:0: 384000000 is greater than the maximum of 200000000 Fix the same. Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> Cc: Rob Herring <robh@xxxxxxxxxx> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx> --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index ab2a1e7955b5..b2d71af9b419 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -388,7 +388,7 @@ sdhc_1: mmc@7824900 { <&gcc GCC_SDCC1_APPS_CLK>, <&xo>; clock-names = "iface", "core", "xo"; - max-frequency = <384000000>; + max-frequency = <200000000>;This might match the binding, but someone put 384000000 there for a reason. Perhaps the binding needs to be updated instead?
I was waiting for getting access to ipq8074 reference manual / documentation. I double-checked and it seems SDCC1 on this SoC does support a max frequency of 384 MHz which is strange as the SDCC2 supports 200 MHz as max frequency instead. Also the eMMC and MMC controllers on other SoCs (i.MX etx( usually support only a max frequency of 200 MHz, so may be we need an exceptional addition to the binding documentation here. @Ulf - what's your view on updating the binding documentation here? I can send a v3 accordingly. Thanks, Bhupesh
mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; -- 2.35.3
