The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane
and one 1-lane.
Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops.
Note that like for SC8280XP, the SA8540P controllers need two or three
interconnect clocks to be enabled.
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
---
drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 7a79bec81bba..699cd8b0f38e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1634,6 +1634,11 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
.ops = &ops_2_4_0,
};
+static const struct qcom_pcie_cfg sa8540p_cfg = {
+ .ops = &ops_1_9_0,
+ .has_ddrss_sf_tbu_clk = true,
+};
+
static const struct qcom_pcie_cfg sc8280xp_cfg = {
.ops = &ops_1_9_0,
.has_ddrss_sf_tbu_clk = true,
@@ -1803,6 +1808,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
+ { .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg },
{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
{ .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
--
2.35.1
